This invention relates to a frequency/voltage conversion circuit used for producing a voltage in accordance with the frequency of a given signal.
When motors are subjected to constant-speed control, the control is carried out in such a manner that a frequency proportional to the number of revolutions of the motor is produced, the thus obtained frequency is converted into a DC voltage, and then a difference voltage between this DC voltage and a reference voltage is fed back. A frequency/voltage conversion circuit is employed in such constant-speed control systems to convert the frequency into a DC voltage.
In the prior art, for example, a frequency/voltage conversion circuit is known which is arranged such that a pulse signal is generated which has a period in accordance with the frequency of a given signal, and there is provided a Flip-Flop which is set upon the rising of the pulse signal. A first capacitor starts to discharge upon the rising of the pulse signal, and a hold signal and first reset signal are generated in accordance with the voltage across the first capacitor while the Flip-Flop is set. The Flip-Flop is reset by a further reset signal when the voltage across the first capacitor reaches a predetermined level, and a second capacitor is provided which starts to discharge when the Flip-Flop is reset, and charge in response to the first reset signal. The voltage across the second capacitor is sampled and held in response to the hold signal, so as to be output as a DC voltage.
In the frequency-voltage conversion circuit of this arrangement, a time constant is determined so that the first capacitor completes its discharging within one period of the input signal having a frequency less than the predetermined frequency. However, if the frequency of the input signal exceeds the predetermined frequency during the start-up of the motor, or due to fluctuations in the load or disturbances while rotating in the stationary state, the period of the pulse signal would become shorter and shorter, whereas the first capacitor, which starts to discharge upon the rising of the pulse signal, has a constant discharge time. Finally, the rising of the next pulse would come on before the potential at the first capacitor reaches the predetermined reference level, and at that time the first capacitor would start to discharge again, thus resulting in a state where the potential at the first capacitor reaches the predetermined reference level during a lapse of the generated pulse. This leads to a drawback such that the Flip-Flop is brought into an input inhibition state with both set and reset inputs being raised to the high level, and hence the operation thereof becomes unstable.